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Product Brief August 2003
WaveLAN TM WL60040 Multimode Wireless LAN Media Access Controller (MAC)
1 Features
protocol including the following: IEEE 802.11a, IEEE 802.11g, and IEEE 802.11h standards, supporting all mandatory and optional CCK and OFDM data rates up to 54 Mbits/s. IEEE 802.11b standard data rates.
! Full implementation of the IEEE(R) 802.11 WMAC
! Full IEEE 802.11 standard is implemented on chip:
Downloadable firmware architecture leads to simple driver solutions.
! Supports 802.11i security encryption algorithms
without impacting device throughput: Advanced Encryption Standard (AES) hardware accelerator operating in Counter Mode (CCM). High-performance hardware acceleration encryption engine supporting Wired Equivalent Privacy (WEP) and 128 RC4. (R) Temporal Key Integrity Protocol (TKIP) per Wi-Fi Protected Access (WPA) hardware accelerator and draft 802.11i standard.
! Flexible external memory expansion (access point
applications): Programmable wait-states for slow external memory. Multiple memory organization up to 4 Mbytes.
! Host interface support of the following:
PCI v2.3 bus mastering 32-bit, 33 MHz transfers with PCI power management. MiniPCI Specification v1.0. CardBus bus mastering 32-bit, 33 MHz transfers v8.0. USB v1.1. PC Card interface supports full 16-bit implementation per PCMCIA release 7.1. Compact Flash CF+ v.1.4.
! Supports BluetoothTM coexistence through a simple
two-wire interface.
! Multiple queue management supports 802.11e
compliant quality of service (QoS).
! Device is capable of low-power operation:
Active mode 35 mA, 8 mA doze, <1 mA sleep.
! Small package footprint: 196-pin FSBGA 12 mm x
12 mm.
! On-chip 64k x 16-bit static RAM supports full IEEE
802.11 client functionality without external memory.
! Flexible modem data interface options:
Multiple baseband processor interfaces (bit, nibble, and byte modes).
! Operation at 3.0 V to 3.6 V single supply. ! Operation ambient temperature: -40 C to +85 C. ! Supports IEEE 1149.1 boundary-scan standard.
! Modem data and modem management interfaces
provide a direct connection to the WaveLAN WL64040 baseband.
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! ! ! ! ! !
Wireless LAN Applications
High data-rate multimode applications. Client cards for notebooks, desktop PCs, and PDAs. Modules with WLAN functionality. Enterprise and home infrastructure devices. High-speed bridges and point-to-multipoint systems. Home entertainment and multimedia systems.
! Supports SPI SEEPROM and I2C(R) SEEPROM
interfaces.
WaveLAN WL60040 Multimode Wireless LAN MAC
Product Brief August 2003
3
Description
The WL60040 MAC is designed to form a complete IEEE 802.11a/IEEE 802.11b/IEEE 802.11g chip set, along with the WL64040 baseband, WL54040 transceiver, and the WL54240 dual-band PA. Using a wide variety of host interfaces, the WL60040 supports the MAC and data buffer management functions and is fully compliant with the IEEE 802.11a, IEEE 802.11b, and IEEE 802.11g WLAN standards. The WL60040 supports high data rates up to 54 Mbits/s while remaining cost-effective. It includes PCI/MiniPCI, CardBus/PCMCIA, PC Card, and Compact Flash support. The device features 1 Mbit of internal memory (RAM It supports the IEEE 802.11b and IEEE 802.11a standardized data rates and the drafted IEEE 802.11g mandatory and optional data rates up to 54 Mbits/s. The WL60040 offers a rich set of exposed interfaces intended to provide flexibility to the system designer in multiple host interface applications. The WL60040 system architecture maps directly to that of the current WL60010 MAC. The major modifications are bus mastering and the addition of a hardware assist engine to support the IEEE 802.11i compliant AES and TKIP security enhancements. Figure 1 details the system architecture and major interfaces.
RX PGA QoS HOST I/F DMA BUS MASTER EMBEDDED PROCESSOR OFDM MDI MMI CCK DAC MULTIMODE BASEBAND PROCESSOR WL64040 TX DUAL-BAND TRANSCEIVER WL54040 QUARTZ XTAL TX BIASING PGC 5 GHz PA DUAL-BAND POWER AMP 2.4 GHz/5 GHz WL54240 MIXED CONTROL SIGNAL CONTROL FREQUENCY SYNTHESIZER ADC LNA RX
AES, WEP, WPA
2.4 GHz PA
T/R & DIVERSITY SWITCH
MINI PCI CARDBUS USB CF+ PC CARD
ON-CHIP RAM
MULTIMODE MAC
WL60040 SEEPROM
Figure 1. WLAN System Block Diagram Showing Major Interfaces The WL60040 directly interfaces with the Agere family of baseband processors, offering a complete end-to-end chip set solution for wireless LAN products. Protocol and PHY support are implemented in firmware to allow custom protocol and IEEE 802.11 PHY transceivers. The WL60040 has been designed to provide maximum performance with minimum power consumption. The FSBGA package provides optimal PC board layout to all of the aforementioned user interfaces. Firmware implements the full IEEE 802.11 wireless LAN MAC protocol. It supports BSS and IBSS operation under DCF. Low-level protocol functions such as RTS/CTS and acknowledgement, fragmentation, defragmentation, and automatic beacon monitoring are handled without host intervention. Active scanning is performed autonomously once initiated by host command. Host interface command and status handshakes allow concurrent operations from multithreaded I/O drivers. Additional firmware functions specific to access point applications are also available. A block diagram detailing the WL60040 device architecture and major interfaces is provided in Figure 2.
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Agere Systems Inc.
Product Brief August 2003
WaveLAN WL60040 Multimode Wireless LAN MAC
3 Description (continued)
EXTERNAL DATA STORAGE FLASH/RAM
EXTERNAL MEMORY INTERFACE (EMI)
WL60040 WMAC PLL
32 kHz XTAL OSCILLATOR
RAM 24K x 16 (CONTROL) MEM CONTROL & DATA PATH
RAM 48K x 16 (DATA)
DEVICE DATA BUS
DEDICATED INSTRUCTION SET CONTROLLER (DISC)
CLK CONTROL TIMERS MMI PORTS MDI
SYSTEM CLOCK
ARBITER AES DMA WEP
PCI BUSMASTER/ CARDBUS PC CARD USB PROTOCOL ENGINE
HOST INTERFACE BLOCK
AES WPA ENGINE ENGINE
WEP MEMORY
USB DMA
USB MEMORY
Figure 2. WL60040 Block Diagram
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Package Information
*
The WL60040 is packaged in a 196 FSBGA package of 12 mm x 12 mm, height 1.45 mm. Only 184 balls may be used for power/ground and signals. The other 12 balls (see Table 7) are not used and should be left unconnected.
12.00 mm 0.80 mm P N M L K J H G F E D C B A 1 2 3 4 5 6 7 8 9 10 11 12 13 14
Figure 3. Pin Layout of 196 FSBGA Used for WL60040, Bottom View
* Height before the solder balls collapse.
Agere Systems Inc.
12.00 mm
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WaveLAN WL60040 Multimode Wireless LAN MAC
Product Brief August 2003
5
Pin Information
The WL60040 signals are grouped by function in Table 1 through Table 5. In addition to the standard (default) pin definitions for each mode, some of the pins are multipurpose and can be programmed to other functions by setting the appropriate bits in device control registers. In the tables below, the pin name column shows the primary function pin name with alternative functions, if applicable, also shown. Signals ending with _B are active-low. Table 1. Host Interface Pins
PCI/CardBus Pin Name* AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 AD23 AD22 AD21 AD20 AD19 AD18 AD17 AD16 AD15 AD14 AD13 AD12 AD11 AD10 AD09 AD08 AD07 AD06 AD05 AD04 AD03 AD02 AD01 AD00 C_BE3_B C_BE2_B C_BE1_B C_BE0_B PAR FRAME_B IRDY_B TRDY_B STOP_B C_BE3_B C_BE2_B C_BE1_B C_BE0_B Alt. Funct. (D10) (D9) (D1) (D8) (D0) (A0) (A1) (A2) (A3) (A4) (A5) (A6) -- (A7) -- -- (IOWR_B) (A9) (IORD_B) -- (OE_B) (CE2_B) -- (D15) (D7) (D13) (D6) (D12) (D5) (D11) (D4) (D3) (REG_B) -- (A8) (CE1_B) -- -- -- -- -- (REG_B) -- (A8) (CE1_B) Pin # K8 J13 N9 M8 P11 L7 L10 J10 P9 L9 L8 N8 M11 K9 M9 L11 P13 P14 L12 M14 J9 J11 M10 K14 J12 N13 M12 K11 L13 K12 N11 K10 L4 H14 H13 H11 N4 K5 M7 H12 M4 L4 H14 H13 H11 Description Multiplexed address/data for PCI and CardBus. Secondary function is used in PC Card mode (selected by BUSSEL). A0--A9 are address, D0--D15 are data. Pull-ups and pull-downs are only active in PC Card mode. They are switched off in any other mode (PCI, CardBus, or USB).
Command/byte enable. Target does not drive C_BE. Pins can be input only.
Parity (even) across AD and C_BE signals. Driven by master for address and write phases; driven by target for read phases. Frame is driven by master to indicate start and duration of a transaction. Initiator ready. Indicates that the initiator (master) is ready to complete the data phase. Target ready. Indicates that the target is ready to complete the data phase. Stop. Indicates that the target request to stop the current transaction. Command/byte enable. Target does not drive C_BE. Pins can be input only.
* All of these interface pins have 5 V tolerant pads.
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Agere Systems Inc.
Product Brief August 2003
WaveLAN WL60040 Multimode Wireless LAN MAC
5 Pin Information (continued)
Table 1. Host Interface Pins (continued)
PCI/CardBus Pin Name DEVSEL_B PERR_B SERR_B Alt. Funct. -- -- (WAIT_B) Pin # N7 P2 P4 Description Device select. Indicates that the target has decoded the address. Parity error. For reporting parity errors during PCI transactions except special cycle. System error, open drain. Used for reporting address parity errors and data parity errors on the special cycle command or any other system error where the result will be catastrophic. PCI clock: provides timing for all transactions. 0 MHz--33 MHz. RST_B is used to bring registers, sequencers, and signals into a consistent state. In PC Card mode, this is RESET: same function but active-high. Initialization device select. Used as chip select during configuration transactions. Used as external power-on reset input in PC Card mode. This pin should be pulled high in Cardbus operation mode. Interrupt output, open drain. (De)assertion is asynchronous to PCICLK. Clock run. Signal to control the PCI clock. Power management enable. Used to request a change in the device or system power state. For PC Card, this pin is STSCHG_B. For CardBus, this pin is STSCHG. Bus grant signal: only needed for PCI/CardBus master. In non-PC Card mode, this pin serves as an external power-on reset input. In PC Card mode, this pin has WE_B functionality. Reserved future use for CardBus. D2 for PC Card. Reserved future use for CardBus. D14 for PC Card. Bus request signal: only needed for PCI/CardBus master. INPACK_B is needed for PC Card. PCI signaling select signal: when this pin is 5 V, 5 V signaling is used, else 3.3 V signaling. PCI cards: connected to pciVIO on the PCI connector. CardBus/Mini PCI: connected to the 3.3 V power rail. PC Card: connected to the 3.3 V power rail. USBPOS USBNEG USBPOS USBNEG L3 M1 USB data signals: connected to terminals DM and DP of the cell.
PCICLK RST_B
-- (RESET)
M3 K6
IDSEL
--
M5
INT_B CLKRUN_B PME_B
(IREQ_B/READY) (IOIS16_B) (STSCHG_B) (STSCHG) WE_B
M6 P6 N5
GNT#
L6
-- -- REQ# PCIVIO
D2 D14 INPACK_B --
L5 N3 N6 P7
* All of these interface pins except USBPOS and USBNEG have 5 V tolerant pads.
Agere Systems Inc.
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WaveLAN WL60040 Multimode Wireless LAN MAC
Product Brief August 2003
5 Pin Information (continued)
Table 2. External Memory Interface Pins
Name and Function Mem MA21 MA20 MA19 MA18 MA17 MA16 MA15 MA14 MA13 MA12 MA11 MA10 MA09 MA08 MA07 MA06 MA05 MA04 MA03 MA02 MA01 MD15 MD14 MD13 MD12 MD11 MD10 MD09 MD08 MD07 MD06 MD05 MD04 MD03 MD02 MD01 MD00 MWE_B MHBS_B MLBS_B MOE_B RAMCS_B NVCS_B Misc OSLP BKCS_B XCSB_B XCSA_B E7 G5 G1 D11 C11 D10 A11 E11 C12 E14 C14 K4 A14 C10 B11 A12 C8 A4 C5 D5 C4 A2 E2 E3 F2 F4 D4 F12 E5 A6 D6 B6 B7 C6 D7 C7 B8 B10 A13 J2 E1 A1 G2 Memory address lines, multiplexed with oscillator sleep, chip selects, and port logic. Pin # Description
VauxPwr 16bdev HOSC HIFISA StrIdle Mem16 NvDs RomDs --
Memory data 15.
Memory data, low byte.
MWEL_B MWEH_B MA00 -- -- BootCS_B
Memory write/read enable signals for single 16 bits. Alternative signals for dual 8 bits or single 8 bits external RAM. Memory output enable. RAM chip select. Boot ROM/nonvolatile chip select.
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Agere Systems Inc.
Product Brief August 2003
WaveLAN WL60040 Multimode Wireless LAN MAC
5 Pin Information (continued)
Table 3. Modem Interface Pins
Name and Function Modem Misc I/O Port TXC TXD RXD RXC XBUSY BTBusy TXRX2 BSEL LED RadioEn PDA MBUSY EDET TXE PHYSLP_B PHYRES WLANBusy PStat SCK SDIO SDI SDS0 SDS1 SDS2 PSwitch TXRX3 TRXC TXRX0 TXRX1 TXRX5 TXR TXRX4 -- TXRX6 TXRX7 UWDET -- -- -- RXE -- SLOT -- -- -- SDDIR PHYCS_B -- -- SDS3 -- -- -- Pin # C2 D12 F9 C3 H2 D13 K1 H3 H1 F10 E10 G12 E12 G11 F11 G10 K2 C13 H10 F5 B14 E9 E6 K3 F3 Description Transmit clock input for WL64040. Transmit/receive clock for MDI nibble and byte mode. Transmit data, receive data. For OFDM, these pins are used as transmit or receive data (half duplex). Transmit busy function; alt: transmit ready. Bluetooth busy signal; Bit 4, MDI byte mode. Bit 2, MDI nibble, or byte mode. Band select LED function; Alt: K-port, octal mode pins. Radio disable switch; Alt: K-port, octal mode pins. PHY data available. Medium busy. Energy detect. Transmit enable. PHY sleep; Alt: receive enable. PHY Reset, FW-controlled through L(2). WLAN busy signal; Alt: slot synchronization, FW-controlled through L(3). Phy status, FW-controlled through L(4). Serial clock MMI. Serial data out MMI. 2 SCL for I C, FW-controlled through J(1). Serial data in MMI/ SDDIR output. Device select5, FW-controlled per J(2) port. Device select0, typically from MMI state machine. PHY memory chip select. Device select1, typically from MMI state machine. Device select2, SDA for I C, FW-controlled through J(5). Modem power switch/device select3. FW-controlled per J(6) port, shared with debug information. Bit 3, MDI nibble, or byte mode.
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K(4) J(7) -- K(2) K(3) K(5) K(6) K(7) L(0) L(1) L(2) L(3) L(4) J(0) J(1) SCL J(2) SDS5 J(3) J(4) J(5) SDA J(6) --
Table 4. Test Interface and Indicator Pins
Name TEST_B SCAN_B BSCANEN TDI TDO TMS TRST_B TCK MCLKOUT Pin # A8 G3 E13 J4 H5 J3 E8 D3 E4 Description Test mode select. This pin is also used to disable the pull-ups/pull-downs (for IDDQ test). Must be externally connected to VDD. Selects between scan (shift) and capture mode: 0 = scan, 1 = capture. Boundary-scan compliance pin: 0 selects debug functionality on BSCAN pins TDI, TDO, TMS, TRST_B and TCK. 1 selects BSCAN functionality on the mentioned pins. Boundary-scan data in. Boundary-scan data out. Boundary-scan mode select. Boundary-scan reset. Boundary-scan clock. MCLK clock output.
Agere Systems Inc.
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WaveLAN WL60040 Multimode Wireless LAN MAC
Product Brief August 2003
5 Pin Information (continued)
Table 5. Power and Ground Pins
Pin Name VDD_USB VSS_USB VDD_32KHZ VSS_32KHZ VDD_PLL VSS_PLL VDD3 VDD4 VDD5 VDD7 VDD8 VDD10 VDD14 VDD18 VDD1 VDD2 VDD6 VDD9 VDD11 VDD12 VDD13 VDD15 VDD16 VDD17 VSS1 VSS2 VSS6 VSS8 VSS9 VSS11 VSS13 VSS14 VSS3 VSS4 VSS5 VSS7 VSS10 VSS12 VSS15 VSS16 VSS17 VSS18 Pin # N1 M2 A9 B9 G13 G14 K13 N2 N14 N12 P12 P8 P3 J14 A3 B12 A7 F1 B1 B2 B3 F13 B13 F14 M13 L14 P5 N10 K7 P1 H9 P10 B4 B5 L1 A10 D1 D14 G9 D2 A5 L2 Description 3.3 V for USB transceiver. Ground for USB transceiver. 3.3 V for 32 kHz oscillator. Ground for 32 kHz oscillator. 3.3 V for PLL. Ground for PLL. 3.3 V for PCI.
3.3 V for other I/O logic.
Ground for PCI.
Ground for other I/O logic.
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Agere Systems Inc.
Product Brief August 2003
WaveLAN WL60040 Multimode Wireless LAN MAC
5 Pin Information (continued)
Table 6. Miscellaneous Pins
Pin Name CKIN XTALA32K XTALB32K* BTBusy WLANBusy LED1 LED0 INTPPOREN BUSSEL1 BUSSEL0

Pin # C1 D9 C9 D13 G10 D8 J5 G4 J1 H4 Clock input. 32 kHz crystal oscillator inputs.
Description
Bluetooth busy signal; Bit 4, MDI byte mode. WLAN busy signal; Alt: slot synchronization, FW-controlled through L(3). LED1, FW-controlled per K(1) port. LED0, FW-controlled per K(0) port. Used to select between external power-on reset (0) or internally generated power-on reset. Host Bus Interface select signals: BS[1] 0 0 1 1 BS[0] 0 1 0 1 Mode 16-bit: PC-Card USB CardBus PCI
* An external 32 kHz signal can also be provided on this pin. LED[1:0] pins characteristics defined as: ISOURCE = 9.4 mA; ISINK = 6.5 mA. BUSSEL[1:0] signals do not have 5 V tolerant pads.
Table 7. Unused Pins
Pin Name VSSNC1, VSSNC2 VSSNC3, VSSNC4 VSSNC5, VSSNC6 VSSNC7, VSSNC8 VSSNC9, VSSNC10 VSSNC11, VSSNC12 Pin # F6, F7 F8, G6 G7, G8 H6, H7 H8, J6 J7, J8 No connections.* Description
* These pins are not connected to anything internally within the chip and should be left unconnected within the board design.
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Electrical Characteristics
Table 8. Operating Conditions
Category Power Supply Range Suspend Current (typ): USB Mode Sleep Current (typ): CardBus/miniPCI Mode PCMCIA Mode Ambient Temperature Value 3.0 V--3.6 V < 0.5 mA 10 mA 2.5 mA Min = -40 C/Max = 85 C USB: Min = 0 C/Max = 85 C
Note: Junction temperature is determined by power dissipation and thermal resistance of the package.
Agere Systems Inc.
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WaveLAN WL60040 Multimode Wireless LAN MAC
Product Brief August 2003
6 Electrical Characteristics (continued)
Table 9. Active Power Dissipation
Mode IEEE 802.11b IEEE 802.11a/b/g CardBus/mPCI 132 149 USB 99 116 PC Card 83 99 Unit mW mW
Table 10. Recommended Operating Condition Limits
Parameter Power Supply Voltage with Respect to Ground Input Voltages Junction Temperature Symbol VDD VIN TJ Min 2.7 VSS - 0.3 -40 Max 3.6 VDD + 0.3 125 Unit V V C
Table 11. Absolute Maximum Ratings*
Parameter Power Supply Voltage with Respect to Ground Input Voltages Junction Temperature Symbol VDD VIN TJ Min -- VSS - 0.3 -40 Max 4.2 VDD + 0.3 125 Unit V V C
* Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operations sections of the data sheet. Exposure to absolute maximum ratings for extended periods can adversely affect device reliability.
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Ordering Information
Part Number WL600402LY-DB Temperature Range C -40 to +85 Package FSBGA196 Packing Tray MOQ 756 Comcode 700054556
Wi-Fi is a registered trademark of Wireless Ethernet Compatibility Alliance, Inc. Bluetooth is a trademark of Bluetooth SIG, Inc. I2C is a registered trademark of Philips Electronics N.V. IEEE is a registered trademark of The Institute of Electrical and Electronics Engineers, Inc.
For additional information, contact your Agere Systems Account Manager or the following: INTERNET: http://www.agere.com E-MAIL: docmaster@agere.com N. AMERICA: Agere Systems Inc., Lehigh Valley Central Campus, Room 10A-301C, 1110 American Parkway NE, Allentown, PA 18109-9138 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA: Agere Systems Hong Kong Ltd., Suites 3201 & 3210-12, 32/F, Tower 2, The Gateway, Harbour City, Kowloon Tel. (852) 3129-2000, FAX (852) 3129-2020 CHINA: (86) 21-5047-1212 (Shanghai), (86) 755-25881122 (Shenzhen) JAPAN: (81) 3-5421-1600 (Tokyo), KOREA: (82) 2-767-1850 (Seoul), SINGAPORE: (65) 6778-8833, TAIWAN: (886) 2-2725-5858 (Taipei) EUROPE: Tel. (44) 1344 296 400
Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. Agere is a registered trademark of Agere Systems Inc. Agere Systems and the Agere logo are trademarks of Agere Systems Inc. WaveLAN is a trademark of Agere Systems Inc.
Copyright (c) 2003 Agere Systems Inc. All Rights Reserved
August 2003
PB03-164WLAN

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